Design of pipelined MIPS Processor with Cache controller using Verilog Implementation

Abstract

The advance of VLSI technology has been the enhancing feature in the appearance of VLSI circuits handling floating point (FP) arithmetic. The different requirements for various processor applications also differ, i.e., some processors have a rich repertoire of functions but results in low performance, while some processors aim at having the highest throughput but use more operations such as multiply and add which produces more latency. For real-time processing requirements, performing a large amount of FP operations are considered as a major bottleneck due to the excessively long run time required. The FP arithmetic typically requires additional operations such as alignment, normalization and rounding, giving rise to some significant increase in terms of area, power consumption and computational latency. Such a problem might be mitigated by employing the fused FP add-subtract and dot-product units specially designed for those dedicated computing-intensive tasks. Rounding concentrates on the critical path and high-speed rounding algorithms are used to increase the performance for floating-point multiplication.

To achieve high performance with minimum increase in hardware, existing rounding algorithms like mantissa, exponent and sign are used to generate two consecutive values in parallel, and compute the rounded product by using these values. In this paper floating point ALU with double precision architecture with register bank for implementing RISC processor will be presented. Floating point arithmetic unit using double precision is planned to construct.

In this paper, the instruction cache and data cache will be taken separately and located in the CPU (Central Processing Unit) core. Write back policy is planned to be used where no replacement algorithm is required. After completing the cache controller design, it will be combined with a pipelined MIPS processor and used in programs execution. Thus, the proposed double precision unit will be used as one of the modules for designing an pipelined MIPS processor. The circuits are designed by Encounter RTL (digital design) using Cadence and the simulation results will be observed using spectre tool.