Isolation Polarity Check In UPF Design Using Clamp Checker

Abstract

Low Power Aware verification became a major concern in the semiconductor industry. The shrinking size of the engineers allowed several approaches to be applied. This has made the process of verifying thepower aware constraints for the design complicated. To approach the power aware verification for complex designs in 2007. Accellera introduced Unified-Power-Format (UPF) (1.0) standards. Later in 2009, IEEE introduced standard UPF 2.0 format which enabled the verification engineers to use inbuild and static and dynamic rules which can be used for validating the power intents and the given specifications of the design.UPF is predominantly used for defining power management and methods which are used for minimizing the power consumption/dissipation in the design. This is used with hardware description languages likeVerilog, System-Verilog and VHDL. The major areas of concerns are simulation, emulation, static or formal verification, logical synthesis, DFT, placement and routing etc.